1. Field of the Invention
The present invention relates to a semiconductor integrated circuit apparatus or more in particular to a semiconductor integrated circuit apparatus having a high speed and low power consumption at the same time.
2. Description of the Related Art
A CMOS circuit decreases in speed with a decrease in voltage. For the speed decrease to be complemented for, the threshold voltage of the MOS transistor (or the MIS transistor) is required to be reduced. The problem, however, is that the power consumption is increased by the subthreshold leakage current of the MOS transistor when the CMOS circuit is not in operation. A solution to this problem is described in IEEE Journal of Solid-State Circuits, Vol. 31, No. 11, November 1996, pp. 1770-1779 (hereinafter referred to as Reference 1).
The technique of Reference 1 is shown in FIG. 5. Reference characters vdd designate a power supply voltage which is 0.9 V in this prior art, vss the ground voltage, vbp is the substrate bias voltage of a PMOS, vbn the substrate bias voltage of a NMOS, numeral 200 a circuit configured with a MOS transistor, numeral 202 a substrate bias control circuit, and numeral 203 a mode signal. Generally, the potential difference between the voltage of the well or the substrate constituting the MOS transistor and the source voltage thereof is defined as the substrate bias. For our purpose, however, the absolute voltage (the potential difference with the ground voltage 0 V) of the well or the substrate constituting the MOS transistor is defined as the substrate bias.
In this conventional circuit, as the substrate bias of the MOS transistor constituting the CMOS circuit, a deeper voltage is applied when the CMOS circuit is not in operation (hereinafter referred to as the standby mode or standby state) than when the CMOS circuit is operating (hereinafter referred to as the active mode or the active state). The term “deeper substrate bias is applied” is defined as “a higher voltage is applied for the PMOS” and “a lower voltage is applied for the NMOS”. When “a shallow substrate bias is applied” is said, on the other hand, it means that “a lower voltage is applied for the PMOS” and “a higher voltage is applied for the NMOS”. These expressions are used in the description that follows.
In the conventional circuit described in Reference 1, voltages of 1.4 V and −0.5 V are applied as the substrate bias voltages of PMOS and NMOS in active mode, respectively, while 4.2 V and −3.3 V are applied to the PMOS and NMOS as the substrate bias voltages thereof in standby mode. When a deep substrate bias is applied thereto, the MOS transistor exhibits a substrate bias effect in which the threshold voltage thereof increases. In standby mode, therefore, the subthreshold leakage current decreases than in active mode.
The reduction in power consumption in standby mode by use of the substrate bias in the conventional circuit has the following problems:                (1) Although the threshold voltage is changed in standby mode and active mode by the substrate bias effect, the dependence of the threshold voltage on the substrate bias generally decreases with the decrease in the gate length (Lg) of the MOS transistor.        (2) Generally, the CMOS circuit operates at higher speed with a smaller substrate bias effect, and therefore, designing a MOS transistor with an increased substrate bias effect in order to reduce the subthreshold leakage current in standby mode is conflicting.        (3) For the threshold voltage to change more between standby mode and active mode, a deeper substrate bias is applied. The application of a deeper substrate bias, however, causes a larger drain-well or well-well potential difference of the MOS transistor, thereby leading to a larger junction leakage current in the PN junction.        
The present inventors have discovered that once a substrate bias to some depth is applied to the a MOS transistor having a small gate oxide thickness (gate insulating film), the leakage current is not decreased even when a deeper substrate bias is applied thereto. Rather, a junction leakage current called the gate-induced drain leakage (GIDL) current comes to flow in the PN junction, often resulting in an increased leakage current for an increased power consumption in standby mode.
FIG. 19 is a diagram showing the gate voltage (Vgs) dependency of the drain current (Id) of the MOS transistor having a small gate oxide thickness. In a region with a large drain-gate voltage, the leakage current called the GIDL current flows from the drain to the substrate.
The curve A indicates the dependency characteristic in the case where the drain voltage (Vds) is 1.8 V and no substrate bias is applied (Vbb=0 V). The drain current (Id) with the gate voltage (Vgs) of 0 is the leakage current flowing while the transistor is in off state. The subthreshold leakage current flows in the case where Vgs is almost 0 V.
The curve B indicates the dependency characteristic in the case where Vds=1.8 V and a small amount of substrate bias is applied, e.g. in the case where a voltage Vbb of −1.5 V is applied to the substrate. In this case, the substrate bias effect reduces the subthreshold leakage current. With the curve B, the magnitude of the leakage current flowing when the transistor is in off state is determined by the subthreshold leakage current.
The curve C indicates the dependency characteristic in the case where Vds is 1.8 V and the substrate bias is applied more deeply, for example, in the case where Vbb=−2.3 V. In this case, the substrate bias effect reduces the subthreshold current on the one hand, while the GIDL current increases on the other hand. For the curve C, the GIDL current is a controlling leakage current flowing when the transistor is in off state. The application of a deeper substrate bias undesirably increases the leakage current with the transistor off as compared with when a shallower bias is applied (curve B).
In this way, with a MOS transistor having a small gate oxide thickness, it has been found that application of a substrate bias deeper than a predetermined level cannot reduce the leakage current but rather increases it due to the GIDL current against the past belief. Depending on the transistor profile (such as the impurities concentration of the diffusion layer), the GIDL current for the MOS transistor having a gate oxide thickness of not more than 5 nm increases to a non-negligible degree, and therefore the range of the substrate bias that can be applied is limited correspondingly. Thus, in the prior art, the effect of reducing the leakage current of the MOS transistor having a small gate oxide thickness is unavoidably limited.                (4) The subthreshold leakage current and the leakage current in the PN junction makes it difficult to conduct the IDDQ test for screening out defective products according to the current flowing in the circuit.        